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WORKSHOP PRESENTATIONS

Opening Pandora’s Box with Fast-CAD
Andrew R. Neureuther
Performance Status of EUV Resist
Chawon Koh
Investigation of Buried Mask Defect Printability in EUV Lithography Through Simulation and Actinic Inspection
Chris H. Clifford
PML2 – Projection Mask-Less Lithography The High Energy ML2 Solution within MAGIC
Christof Klein
EUVL - yes, we can!
Hans meiling
Dual damascene processing using multilevel step and flash imprint lithography
Kane Jen

3-Dimensional ICs: Motivation, Performance Analysis and Technology
Krishna Saraswat
Source Mask Optimization at Full Chip Scale using Inverse Lithography Technology (ILT) based on Level Set Methods
Linyong Pang
Update on REBL status for Direct Write Electron Beam Lithography
Mark McCord,
The total measurement approach to lithography measurement and characterization
Nigel Smith
3D IC Design and Applications
Paul Franzon
Complexity of data preparation and proximity effects corrections in ebeam maskless lithography
Serdar Manakli
Challenges and Alternatives for EUV Reticle Inspection
Sterling Watson
Pushing the limit of optical lithography for advanced logic device
Takayuki Uchiyama
EUVL Mask Inspection and Metrology Capability
Tsuneo Terasawa
Computational Lithography:
Moore Bang For Your Buck
Vivek Singh
Metrology and Inspection Challenges for 22nm Wafer and Mask
Wolf Staud
Electron Beam Direct Writing technology for the metal interconnect at 65nm node and beyond
Yoshinori Kojima
Why Computational Lithography?
Yuri Granik