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TECHNICAL PROGRAM

2007 LITHOGRAPHY TECHNICAL SESSIONS

Advanced Publication of Program Topics and Invited Speakers
Exact presentation schedule is subject to change
More detail and updates can be found here at www.lithoworkshop.org

Prof. Fabian Pease and Dr. Juan Maldonado
Stanford University
Workshop Program Co-Chairmen

Keynote Speakers

Steve Chou, Princeton University
"Nanoimprint, Guided Self-Assembly and Beyond"

Joseph Gordon, IBM
"Directed Self Assembly"

Mike Lercel, Sematech
"Design for Manufacturability "

Burn Lin, TSMC
"Three D’s in Immersion Lithography: Depth of Focus, Defects, and Device Performance"

Hank Smith, MIT
"Commercialization of Maskless Zone-Plate-Array Lithography (ZPAL), and its Extension to the Limits of Lithography"

Technical Sessions and Invited Speakers

193 nm Lithography
Chair: Donis Flagello, ASML
Co-chair: Tatsuhiko Higashiki, Toshiba
Soichi Owa, Nikon
"Recent history and future outlook of NGL – why did immersion succeed where 157nm failed and what’s next?"
Takayuki Uchiyama, NEC
"Current status and prospects of lithography for logic device mass production"
Bryan Rice, SEMATECH
"Materials Advances in High Index 193nm Immersion Lithography"
Donis Flagello, ASML
"The Future of Optical Lithography - Extinction or Evolution"
Tatsuhiko Higashiki, Toshiba
"Status and future lithography for sub hp32nm device"

Computational Lithography and DFM
Chair: Bob Socha, ASML
Co-chair: Shigeki Nojima, Toshiba
Yan Borodovsky, Intel
"Enabling Moore's Law through Computational Lithography"

Shigaki Nojima, Toshiba
"Layout and OPC verification scheme in production"
Yorick Trouiller, ST Microelectronics
"RET solutions for System On Chip : from 120nm to 32nm node, an evolutionary scenario"
Cyrus Tabery, AMD
"Design rule selection and optimization via computational lithography : an integrated perspective to technology development"


Electron Beam Lithography
Chair: Tim Groves, State University of New York, Albany
Co-chair: Serge Tedesco, CEA-LETI
Laurent Pain, CEA-LETl
"How to succeed in introducing the cost attractive ML2 technology into industry?"
Akio Yamada, Advantest
"Present status of Development of Multi-Column Cell System with CP Technology"
Zhi Liu, Juan Maldonado, Piero Pianetta and RFW Pease, Stanford University
"Search for Bright Electron Source"
Eric Munro, Munro's Electron Beam Software Ltd.
"Aberration Correction in Electron Beam Lithography"

Resist Technology
Chair: Robert Brainard, State University of New York, Albany
Co-chair: David Van Steenwinckel, NXP Semiconductors
Gregg Gallatin, Gallatin Consulting,
"A Comprehensive Model of Photoresist Behaviorr"
Tom Wallow, AMD,
"Patterning Materials in Future Semiconductor Technology Nodes: Opportunities and Limits"

Seiichi Tagawa, Osaka University
Kyoko Kojima, Hitachi,
"Negative-Tone Molecular Resist"

Mask Technology
Chair: Ben Eynon, SEMATECH
Co-chair: Naoya Hayashi, Dai Nippon Printing
Ben Eynon, SEMATECH (Samsung)
"EUVL Mask Infrastructure Development"
Roxann Engelstad, Univ. of Wisconsin, Madison
"The Mechanics of Electrostatic Chucking"
Will Conley, Freescale Semiconductor
"The Good, the Bad and the Ugly of High Transmission Masks"

Inspection and Metrology
Chair: Mark McCord, KLA-Tencor
Co-chair: Yuichiro Yamazaki, Toshiba
John Allgair, SEMATECH
Shunsuke Koshihara, Hitachi High-Technologies Corporation
"The challenge to new metrology world by CD-SEM and Design"
Stan Stokowski, KLA-Tencor
"Mask Inspection in a Shrinking World: Rough Road Ahead?"
Tony DiBiase, KLA-Tencor
"Metrology and Inspection Challenges facing the introduction of Pitch Splitting and DPL"

Self Assembly
Chair: Paul Nealey, University of Wisconsin at Madison
Co-Chair: Tom Albrecht, Hitachi Global Systems
Ricardo Ruiz, Hitachi Global Storage Systems
"Guiding Self-Assembly for High Density Patterning"
Juan de Pablo, Univ. of Wisconsin, Madison
"Directed assembly of block copolymers on chemically patterned substrates"
Mike Garner, Intel
Yehiel Gotkis, KLA-Tencor
"Interfacial Dynamic Mesoscopic Structuring As a Highly Probable Origin of the LER Mysterious “Fundamental 5nm-Limit"

EUV Lithography
Chair: Bruno LaFontaine, AMD
Co-chair: Kurt Ronse, IMEC
David Brandt, Cymer
"Laser Produced Plasma Source Development for HVM"
Jeroen Jonkers, Philips EUV
"DPP EUV Sources"
Steve Renwick, Nikon
"Nikon EUVL tool development status"
Kevin Cummings, ASML
"EUV Lithography"
Minoru Sugawara, Sony
"Readiness to develop mask pattern correction tools in EUV lithography"
Kurt Ronse, IMEC
"EUVL status at IMEC"

New Applications
Chair: Andy Neureuther, Berkeley
Co-chair: Chris Wilkinson, University of Glasgow
Emily True, Ultratech
"Lithography for 3D Chip Packaging Applications"
Bruce McWilliams, Tessera
"3D Lithography Processes and Equipment for Multi-Device Integration Applications"

Imprint Lithography
Chair: S.V. Sreenivasan, Molecular Imprints,
Co-chair: Steven Chou, Princeton University
Naoya Hayashi, DNP
"UV-NIL template for the 22nm node and beyond"
Mark Hart, IBM
"Step-and-Flash Imprint Lithography for Storage-Class-Memory"
S.V. Sreenivasan, Molecular Imprints
"UV Imprint Tool and Process Technology: Status and Challenges"
Tom Albrecht, Hitachi Global Systems
"Nanoimprinted Patterned Media: The Next Major Technical Transition for the Hard Disk Industry"

2007 LITHOGRAPHY WORKSHOP POSTER SESSIONS

The 2007 Lithography Workshop will sponsor two poster sessions. Below is the poster list as of October 1, 2007

To Submit a Poster paper, please submit an abstract to:
Dr. Juan Maldonado (jrmaldonado@stanford.edu)

or
Prof. Fabian Pease (pease@cis.stanford.edu)

POSTERS

Marty Peckerar University of Maryland Issues in Computational Lithography
Tor Sandstrom, Christer Rydberg Micronic Laser Systems AB Comprehensive LER modeling
John Burnett NIST High Index DeepUV Optical Materials
Alexander Tritchkov Mentor Graphics Model based SRAF insertion
David Owen Ultratech CGS Stress Metrology for the Characterization of Lithography Misalignment
Tejas Jhaveri Carnegie Mellon Extending Single Patterning through the 32 nm technology
Paolo Piacentini ST Microelectronics Evaluation and qualification of a sokudo RF3 immersion track
S. Sunaoshi Nuflare Extension of e-beam writing update
Bert Jan Kampherbeek Mapper Lithography Update on Mapper multibeam
Greg Hughes Sematech Mask and Wafer COO into the Murky Feature
Joseph Gordon Toppan Photomask After the Honeymoon - Haze, an industry problem and collective solutions
Linard Karklin Sagantec A lithography aware design optimization using foundry-certified models and hotspot detection
Masaki Yamabe ASET Optimization of MDP, Mask Writing and Mask Inspection for Mask Manufacturing and Cost Reduction
Mordy Rothschild MIT/Lincoln Labs Grid-Based Interference Double Exposure Lithograhy (GRINDEL)
Takao Utsumi Nanolith LLC LEPPL-To Evaluate and Succeed Optical Lithography Beyond 32nm/Hp
Pieter Kruit Delft University Massively parallel electron beam inspection
Pieter Kruit Delft University Sub 10nm electron beam lithography